LLVM-Based WCET Analysis Tool
Academic-grade Worst-Case Execution Time analysis using LLVM infrastructure for embedded systems and real-time applications
Accurate WCET estimation using LLVM intermediate representation for precise timing analysis
Advanced CFG construction with loop detection and bound extraction
Platform-specific instruction timing with IPET solver integration
Support for RMA and EDF scheduling with response time analysis
13+ platform configurations including ARM Cortex and RISC-V
Graphviz export and Gantt chart generation for schedule analysis
Loading platforms from GitHub...
LALE uses a 4-layer hierarchical configuration system:
ISA → Core → SoC → Board
Each layer inherits from the previous and can override parameters.
This allows easy board variants with the same SoC but different frequencies.
Base instruction set architecture with instruction timings
[isa]
name = "ARMv7E-M"
architecture = "ARM"
word_size = 32
endianness = "little"
[instruction_timings]
alu = 1 # ADD, SUB, MOV, etc.
shift = 1 # LSL, LSR, ASR, ROR
mul = 1 # MUL (single cycle on Cortex-M4)
div = 12 # SDIV, UDIV
load = 2 # LDR
store = 2 # STR
branch = 1 # B, BL
branch_cond = 1 # BEQ, BNE, etc. (predicted taken)
branch_miss = 3 # Branch misprediction penalty
CPU core microarchitecture details
[core]
name = "Cortex-M4"
isa = "armv7e-m"
[core.pipeline]
stages = 3
type = "in-order"
[core.cache.instruction_cache]
size_kb = 16
line_size_bytes = 32
associativity = 4
replacement_policy = "LRU"
hit_latency = 1
miss_latency = 10
[core.memory]
load_buffer_size = 4
store_buffer_size = 4
[core.memory.latency]
type = "fixed"
cycles = 10
System-on-Chip with frequency and memory regions
[soc]
name = "STM32F746"
core = "cortex-m7"
cpu_frequency_mhz = 216
[[soc.memory_regions]]
name = "FLASH"
start_address = "0x08000000"
size_bytes = 1048576
type = "ROM"
wait_states = 7
[[soc.memory_regions]]
name = "SRAM1"
start_address = "0x20000000"
size_bytes = 327680
type = "RAM"
wait_states = 0
Specific board implementation with inheritance
[board]
name = "STM32F746-Discovery"
description = "STMicroelectronics STM32F746G-DISCO"
inherits = "socs/stm32f746" # Inherit from SoC config
[board.clock]
frequency_mhz = 216 # Can override SoC frequency
crystal_mhz = 25
[board.memory.flash]
start_address = "0x08000000"
size_bytes = 1048576
[board.memory.sram]
start_address = "0x20000000"
size_bytes = 327680
Users can define custom boards in config/boards/user/
# config/boards/user/my-custom-board.toml
[board]
name = "My Custom Board"
inherits = "socs/stm32h743"
[board.clock]
frequency_mhz = 400 # Override frequency
# Add custom memory regions
[[board.memory_regions]]
name = "EXTERNAL_SDRAM"
start_address = "0xC0000000"
size_bytes = 8388608
type = "RAM"
config/isa/# List available boards
lale list-boards
# Validate board configuration
lale validate-board platforms/stm32f746-discovery
# Export resolved configuration
lale export-board platforms/stm32f746-discovery > resolved.toml
# Run analysis with board config
lale analyze ./data/firmware --board platforms/stm32f746-discovery